1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, it relates to a semiconductor memory device having a structure capable of supplying a stable power supply voltage.
2. Description of the Prior Art
The structure of a conventional semiconductor memory device 9000 is described with reference to FIG. 20. The semiconductor memory device 9000 shown in FIG. 20 has an internal circuit group 990 including memory cells and a synchronous circuit 995 generating an internal clock. The synchronous circuit 995 is driven by an operation start trigger signal and generates the internal clock deciding operation timing in the internal circuit group 990. The synchronous circuit 995 is formed by a PLL circuit or the like, for example.
As shown in FIG. 20, the synchronous circuit 995 and the internal circuit group 990 share a power source 900, to operate with a power supply voltage received from the power source 900 and a ground voltage GND as operating voltages.
The operating voltages must be stable so that the synchronous circuit 995 performs a synchronous operation in high precision.
When the internal circuit group 990 operates, however, noise originates following current consumption to disadvantageously swing the power supply voltage. In the structure of the conventional semiconductor memory device 9000, therefore, precision of the internal clock is disadvantageously damaged following the internal operation.
When the internal circuit group 990 is defective, the power supply voltage or a signal voltage similarly swings. Therefore, influence following a failure of the internal circuit group 990 must be suppressed not only for circuits in the same chip but also for another device connected through the same wire.
Accordingly, an object of the present invention is to provide a semiconductor memory device having a large operation margin in a high-frequency operation by supplying a stable power supply voltage.
Another object of the present invention is to provide a semiconductor memory device capable of guaranteeing a stable operation of an apparatus connected through the same wire while suppressing influence exerted by a failure.
A semiconductor memory device according to an aspect of the present invention comprises an internal circuit including a memory cell array, a voltage supply node, a synchronous circuit operating on the basis of an operating voltage received from the voltage supply node for generating an internal clock deciding operation timing of the internal circuit, a power source for supplying a voltage to the internal circuit and the voltage supply node, and a voltage stabilizing circuit stabilizing the voltage of the voltage supply node.
Preferably, the voltage stabilizing circuit includes a detection circuit detecting change of the voltage of the voltage supply node and a circuit supplying the voltage from the power source to the voltage supply node in response to an output of the detection circuit.
According to the aforementioned semiconductor memory device, therefore, a precise synchronous operation is guaranteed by arranging a circuit eliminating power supply noise and supplying a stable operating voltage to the synchronous circuit also when the synchronous circuit and the internal circuit use the same power source.
Preferably, the power source includes a first power source corresponding to a first voltage and a second power source supplying a second voltage lower than the first voltage, the voltage supply node includes a first voltage supply node corresponding to the first power source and a second voltage supply node corresponding to the second power source, the voltage stabilizing circuit is provided between the first power source and the first voltage supply node, and the semiconductor memory device further comprises a dummy current generation circuit feeding a dummy current from the first voltage supply node to the second voltage supply node at prescribed timing. More preferably, the dummy current generation circuit includes a transistor provided between the first voltage supply node and the second voltage supply node and rendered conductive at prescribed timing.
The dummy current is fed between the power source supplying an internal voltage to the synchronous circuit and a GND side. Thus, the operation of the detection circuit (differential amplifier) arranged on the side of the power source for detecting change of the operating voltage is stabilized.
Preferably, the power source includes a first power source corresponding to a first voltage and a second power source supplying a second voltage lower than the first voltage, the voltage supply node includes a first voltage supply node corresponding to the first power source and a second voltage supply node corresponding to the second power source, the voltage stabilizing circuit is provided between the first power source and the first voltage supply node, and the semiconductor memory device further comprises a high impedance element raising the impedance between the second voltage supply node and the second power source.
A high impedance component is arranged on the GND side, thereby preventing a ground voltage from mixture with noise.
Preferably, the semiconductor memory device further comprises a voltage change circuit provided between the first voltage supply node and the second voltage supply node for changing the voltages of the first and second voltage supply nodes in the same direction. More preferably, the voltage change circuit includes a capacitive element provided between the first voltage supply node and the second voltage supply node.
The operating voltage of the synchronous circuit can be kept constant by changing the power source side and the GND side in the same direction.
More preferably, the semiconductor memory device further comprises a filter provided between the power source and the voltage stabilizing circuit.
A more stable operating voltage can be supplied to the synchronous circuit by serially connecting the filters between the power source and the synchronous circuit.
A semiconductor memory device according to another aspect of the present invention comprises a pin, an internal circuit, including a memory cell array, operating on the basis of an input from the pin, and a leakage current prevention circuit provided between the pin and the internal circuit for detecting a leakage current from the internal circuit and electrically disconnecting the pin and the internal circuit from each other.
Preferably, the leakage current prevention circuit includes a detection circuit detecting change of an operating voltage of the internal circuit following the leakage current, and a circuit electrically disconnecting the pin and the internal circuit from each other in response to an output of the detection circuit.
Therefore, the aforementioned semiconductor memory device detects an abnormal current (leakage current) generated in the internal circuit and disconnects the pin and the internal circuit from each other. Thus, influence exerted on an external device by the leakage current can be suppressed.
More preferably, the circuit includes a voltage supply circuit supplying an operating voltage to the internal circuit on the basis of a voltage supplied from the pin, and the voltage supply circuit stops supply of the operating voltage to the internal circuit in response to the output of the detection circuit.
Operations of another chip using the same power supply line can be guaranteed by stopping supply of the operating voltage on the basis of a result of detection of the leakage current.
A semiconductor memory device according to still another aspect of the present invention comprises a pin receiving an input from an external device, an internal circuit, including a memory cell array, operating in response to an input from the pin in a normal mode, a voltage supply node, a synchronous circuit operating on the basis of an operating voltage received from the voltage supply node for generating an internal clock deciding operation timing of the internal circuit, and a voltage supply control circuit supplying a voltage from the pin to the voltage supply node in a test mode.
Thus, the aforementioned semiconductor memory device employs the pin used in the normal mode as a power supply pin for the synchronous circuit in the test mode. When a plurality of chips receive the same signal or voltage through the same signal line or power supply line and a leakage current is generated in any of the chips, for example, reduction of the voltage level of the signal line or the power supply line can be prevented by stopping activation of circuits included in the defective chip.
Preferably, the pin includes a first pin corresponding to a first voltage and a second pin supplying a second voltage lower than the first voltage, the voltage supply node includes a first voltage supply node corresponding to the first pin and a second voltage supply node corresponding to the second pin, and the voltage supply control circuit includes a first voltage supply control circuit supplying the voltage from the pin to the first voltage supply node in the test mode and a second voltage supply control circuit supplying the voltage from the pin to the second voltage supply node in the test mode. More preferably, the first voltage supply control circuit operates to stabilize the voltage of the first voltage supply node, and the second voltage supply control circuit operates to stabilize the voltage of the second voltage supply node.
The operating voltage can be stably supplied to the synchronous circuit in the test mode by providing control circuits for supplying the voltage on a power supply side and a GND side respectively.
Preferably, the voltage supply control circuit includes a generation circuit generating a prescribed signal in the test mode, and a switching circuit supplying the input from the pin to the synchronous circuit and an output of the generation circuit to the internal circuit respectively in the test mode while supplying the input from the pin to the internal circuit in the normal mode. More preferably, the switching circuit includes a first switch provided between the pin and the synchronous circuit and turned on in the test mode, a second switch provided between the pin and the internal circuit and turned on in the normal mode, and a third switch provided between the generation circuit and the internal circuit and turned on in the test mode.
In the test mode, the input received from the pin can be supplied to the synchronous circuit as a power supply voltage by employing the internally generated signal in place of a signal received from the normally used pin.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.